The present invention relates to a semiconductor integrated circuit device which matches the trend toward further miniaturization.
As shown in FIG. 27, a conventional method for designing a semiconductor integrated circuit device has produced layout data based on a design rule which is uniform throughout a chip. Layout data is uniquely determined such that the difference between an expected value and a finished physical size after patterning, each of which is based on the layout data, falls within an error tolerance for the expected value.
Specifically, if a chip surface includes a region for which first OPC (optical proximity correction) data falling within an error tolerance for a first standard value cannot be produced, second layout data based on a second layout design rule and having a second expected value is redetermined uniquely not only for the region but also for all placement regions, whereby the semiconductor integrated circuit device is redesigned. Here, second OPC data is produced by correcting the second layout data such that the difference between a second expected value and an expected finished size after patterning, each of which is based on the second layout data, falls within an error tolerance for the first standard value.
As design sizes are reduced increasingly year after year, however, a chip designing process performed by using one layout design rule for one chip encounters the following problems.
The layout design rule which is 0.13 μm in the year 2001 is expected to become 0.10 μm in the year 2005. If design is to be performed in accordance with the layout design rule of 0.10 μm, a fabrication process requires a patterning accuracy on the order of several tens of nanometers.
In that case, it will become extremely difficult to control variations in patterning accuracy to several tens of nanometers by considering each of variations in patterning accuracy in the fabrication process, which are dependent on the regions (portions) of the principal surface of a wafer, the relationship between the regions (portions) of one chip and layout densities therein, and the like.
If a design rule also considering variations in patterning accuracy is used, a design margin is reduced dramatically so that the yield rate is reduced significantly. As a consequence, the trend toward further miniaturization drastically increases the manufacturing cost for a chip.